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hy5du28422t hy5du28822t HY5DU281622T 2nd 128m ddr sdram hy5du28422t hy5du28822t HY5DU281622T revision 1.3 april 2001 rev. 1.3 / apr. 2001 this document is a general product description and is subject to change without notice.
rev. 1.3 / apr. 2001 2 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram contents 1. 128m ddr sdram brief information --------------------------------------------------------------------- 3 1.1 description 1.2 feature 1.3 ordering information 2. pin & pkg information --------------------------------------------------------------------------------------- 4 2.1 pin configuration 2.2 pin description 2.3 pkg physical dimension 3. functional block diagram ----------------------------------------------------------------------------------- 7 4. command truth table ---------------------------------------------------------------------------------------- 8 4.1 simplified command truth table 4.2 write mask truth table 4.3 operation command truth table 4.4 cke function truth table 5. function description ---------------------------------------------------------------------------------------- 15 5.1 simplified state diagram 5.2 power up sequence and device initialization 5.3 mrs / emrs definition 5.4 device operation 6. absolute maximum rating -------------------------------------------------------------------------------- 33 7. dc operating condition ------------------------------------------------------------------------------------- 33 8. dc characteristics -------------------------------------------------------------------------------------------- 34 9. ac operating test condition ------------------------------------------------------------------------------ 35 10. ac characteristics ------------------------------------------------------------------------------------------ 36 11. input / output capacitance & output load circuit ---------------------------------------------- 38 12. output drive characteristics ---------------------------------------------------------------------------- 39 12.1 full strength drive 13. timing diagram --------------------------------------------------------------------------------------------- 43
description the hynix hy5du28422, hy5du28822 and hy5du281622 are a 134,217,728-bit cmos double data rate(ddr) syn- chronous dram, ideally suited for the main memory applications which requires large memory density and high band- width. the hynix 128mb ddr sdrams offer fully synchronous operations referenced to both rising and falling edges of the clock. while all addresses and control inputs are latched on the rising edges of the ck (falling edges of the /ck), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. the data paths are inter- nally pipelined and 2-bit prefetched to achieve very high bandwidth. all input and output voltage levels are compatible with sstl_2. features ? v dd , v ddq = 2.5v +/- 0.2v ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock inputs (ck, /ck) operation ? double data rate interface ? source synchronous - data transaction aligned to bidirectional data strobe (dqs) ? x16 device has two bytewide data strobes (udqs, ldqs) per each x8 i/o ? data outputs on dqs edges when read (edged dq) data inputs on dqs centers when write (centered dq) ? on chip dll align dq and dqs transition with ck transition ? dm mask write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 2 and 2.5 supported ? programmable burst length 2 / 4 / 8 with both sequential and interleave mode ? internal four bank operations with single pulsed ras ? auto refresh and self refresh supported ? 4096 refresh cycles / 64ms ? jedec standard 400mil 66pin tsop-ii with 0.65mm pin pitch ? full strength driver option controlled by emrs ordering information part no. configuration power hy5du28422t-x* 32mx4 standard hy5du28422lt-x* 32mx4 low power hy5du28822t-x* 16mx8 standard hy5du28822lt-x* 16mx8 low power HY5DU281622T-x* 8mx16 standard hy5du281622lt-x* 8mx16 low power hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram rev. 1.3 / apr. 2001 3 operating frequency * x means speed grade ** jedec specification compliant grade cl2 cl2.5 remark** - h 125mhz 133mhz ddr266b - l 100mhz 125mhz ddr200
rev. 1.3 / apr. 2001 4 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram pin configuration row and column address table items 32mx4 16mx8 8mx16 organization 8m x 4 x 4banks 4m x 8 x 4banks 2m x 16 x 4banks row address a0 - a11 a0 - a11 a0 - a11 column address a0-a9, a11 a0-a9 a0-a8 bank address ba0, ba1 ba0, ba1 ba0, ba1 auto precharge flag a10 a10 a10 refresh 4k 4k 4k 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 nc vddq ldqs nc vdd dnu ldm /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 nc vssq udqs nc vref vss udm /ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc nc vddq nc nc vdd dnu nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc nc vddq nc nc vdd dnu nc /we /cas /ras /cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc nc vssq dqs nc vref vss dm /ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss x16 x8 x4 x4 x8 x16 400mil x 875mil 66pin tsop -ii 0.65mm pin pitch
rev. 1.3 / apr. 2001 5 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram pin description pin type description ck, /ck input clock: ck and /ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power down and self refresh operation (all banks idle), or active power down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit, and for output disable. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck and cke are disabled during power down. input buffers, excluding cke are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. /cs input chip select : enables or disables all inputs except ck, /ck, cke, dqs and dm. all com- mands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or pre- charge command is being applied. a0 ~ a11 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read/write commands, to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op code during a mode register set command. ba0 and ba1 define which mode register is loaded during the mode register set command (mrs or emrs). /ras, /cas, /we input command inputs: /ras, /cas and /we (along with /cs) define the command being entered. dm (ldm,udm) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. for the x16, ldm corresponds to the data on dq0-q7; udm corre- sponds to the data on dq8-q15. dqs (ldqs,udqs) i/o data strobe: output with read data, input with write data. edge aligned with read data, centered in write data. used to capture write data. for the x16, ldqs corresponds to the data on dq0-q7; udqs corresponds to the data on dq8-q15. dq i/o data input / output pin : data bus v dd /v ss supply power supply for internal circuits and input buffers. v ddq /v ssq supply power supply for output buffers for noise immunity. v ref supply reference voltage for inputs for sstl interface. nc nc no connection.
rev. 1.3 / apr. 2001 6 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram 10.26 (0.404) 10.05 (0.396) 11.94 (0.470) 11.79 (0.462) 22.33 (0.879) 22.12 (0.871) 1.194 (0.0470) 0.991 (0.0390) 0.65 (0.0256) bsc 0.35 (0.0138) 0.25 (0.0098) 0.15 (0.0059) 0.05 (0.0020) base plane seating plane 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047) 0 ~ 5 deg. unit : mm(inch) package information 400mil 66pin thin small outline package
rev. 1.3 / apr. 2001 7 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram command decoder clk / clk cke / cs / ras / cas / we dm address buffer add bank control 8 mx4/bank0 column decoder column address counter sense amp 2 - bit prefetch unit 8 mx4/bank1 8 mx4/bank2 8 mx4/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2 - bit prefetch unit ds dq [0:3] 8 4 4 8 clk_dll ba0, ba1 functional block diagram (32mx4) 4banks x 8mbit x 4 i/o double data rate synchronous dram
rev. 1.3 / apr. 2001 8 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram command decoder clk / clk cke / cs / ras / cas / we dm address buffer add bank control 4 mx8/bank0 column decoder column address counter sense amp 2 - bit prefetch unit 4 mx8/bank1 4 mx8/bank2 4 mx8/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver dqs clk /clk ds write data register 2 - bit prefetch unit ds dq [0:7] 16 8 8 16 clk_dll ba0,ba1 functional block diagram (16mx8) 4banks x 4mbit x 8 i/o double data rate synchronous dram
rev. 1.3 / apr. 2001 9 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram command decoder clk / clk cke / cs / ras / cas / we ldm address buffer add bank control 2 mx16/bank0 column decoder column address counter sense amp 2 - bit prefetch unit 2 mx16/bank1 2 mx16/bank2 2 mx16/bank3 mode register row decoder input buffer output buffer dll block mode register data strobe transmitter data strobe receiver ldqs, udqs clk /clk ldqs udqs write data register 2 - bit prefetch unit ds dq[0:15] 32 16 16 32 clk_dll ba0, ba1 udm functional block diagram (8mx16) 4banks x 2mbit x 16 i/o double data rate synchronous dram
rev. 1.3 / apr. 2001 10 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram simplified command truth table command cken-1 cken cs ras cas we addr a10/ ap ba note extended mode register set h x l l l l op code 1,2 mode register set h x l l l l op code 1,2 device deselect h x h x x x x 1 no operation l h h h bank active h x l l h h ra v 1 read h x l h l h ca l v 1 read with autoprecharge h 1,3 write h x l h l l ca l v 1 write with autoprecharge h 1,4 precharge all banks h x l l h l x h x 1,5 precharge selected bank l v 1 read burst stop h x l h h l x 1 auto refresh h h l l l h x 1 self refresh entry h l l l l h x 1 exit l h h x x x 1 l h h h precharge power down mode entry h l h x x x x 1 l h h h 1 exit l h h x x x 1 l h h h 1 active power down mode entry h l h x x x x 1 l v v v 1 exit l h x 1 note : 1. ldm/udm states are don?t care. refer to below write mask truth table. 2. op code(operand code) consists of a0~a11 and ba0~ba1 used for mode register setting duing extended mrs or mrs. before entering mode register set mode, all banks must be in a precharge state and mrs command can be issued after trp period from prechagre command. 3. if a read with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+trp). 4. if a write with autoprecharge command is detected by memory component in ck(n), then there will be no command presented to activated bank until ck(n+bl/2+1+tdpl+trp). last data-in to prechage delay(tdpl) which is also called write recovery time (twr) is needed to guarantee that the last data has been completely written. 5. if a10/ap is high when precharge command being issued, ba0/ba1 are ignored and all banks are selected to be precharged. ( h=logic high level, l=logic low level, x=don?t care, v=valid data input, op code=operand code, nop=no operation )
rev. 1.3 / apr. 2001 11 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram write mask truth table function cken-1 cken cs , ras , cas , we dm addr a10/ ap ba note data write h x x l x 1 data-in mask h x x h x 1 note : 1. write mask command masks burst write data with reference to ldqs/udqs(data strobes) and it is not related with read data. in case of x16 data i/o, ldm and udm control lower byte(dq0~7) and upper byte(dq8~15) respectively.
rev. 1.3 / apr. 2001 12 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram operation command truth table-i current state /cs /ras /cas /we address command action idle h x x x x dsel nop or power down 3 l h h h x nop nop or power down 3 l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4 l h l l ba, ca, ap write/writeap illegal 4 l l h h ba, ra act row activation l l h l ba, ap pre/pall nop l l l h x aref/sref auto refresh or self refresh 5 l l l l opcode mrs mode register set row active h x x x x dsel nop l h h h x nop nop l h h l x bst illegal 4 l h l h ba, ca, ap read/readap begin read : optional ap 6 l h l l ba, ca, ap write/writeap begin write : optional ap 6 l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall precharge 7 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 read h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst terminate burst l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap illegal l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal 4 l h l h ba, ca, ap read/readap term burst, new read:optional ap 8 l h l l ba, ca, ap write/writeap term burst, new write:optional ap
rev. 1.3 / apr. 2001 13 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram operation command truth table-ii current state /cs /ras /cas /we address command action write l l h h ba, ra act illegal 4 l l h l ba, ap pre/pall term burst, precharge l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 read with autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write autopre- charge h x x x x dsel continue burst to end l h h h x nop continue burst to end l h h l x bst illegal l h l h ba, ca, ap read/readap illegal 10 l h l l ba, ca, ap write/writeap illegal 10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 pre- charge h x x x x dsel nop-enter idle after trp l h h h x nop nop-enter idle after trp l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall nop-enter idle after trp l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11
rev. 1.3 / apr. 2001 14 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram operation command truth table-iii current state /cs /ras /cas /we address command action row activating h x x x x dsel nop - enter row act after trcd l h h h x nop nop - enter row act after trcd l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,9,10 l l h l ba, ap pre/pall illegal 4,10 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write recovering h x x x x dsel nop - enter row act after twr l h h h x nop nop - enter row act after twr l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal l h l l ba, ca, ap write/writeap illegal l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 write recovering with autopre- charge h x x x x dsel nop - enter precharge after tdpl l h h h x nop nop - enter precharge after tdpl l h h l x bst illegal 4 l h l h ba, ca, ap read/readap illegal 4,8,10 l h l l ba, ca, ap write/writeap illegal 4,10 l l h h ba, ra act illegal 4,10 l l h l ba, ap pre/pall illegal 4,11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 refreshing h x x x x dsel nop - enter idle after trc l h h h x nop nop - enter idle after trc l h h l x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11
rev. 1.3 / apr. 2001 15 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram operation command truth table-iv note : 1. h - logic high level, l - logic low level, x - don?t care, v - valid data input, ba - bank address, ap - autoprecharge address, ca - column address, ra - row address, nop - no operation. 2. all entries assume that cke was active(high level) during the preceding clock cycle. 3. if both banks are idle and cke is inactive(low level), then in power down mode. 4. illegal to bank in specified state. function may be legal in the bank indicated by bank address(ba) depending on the state of that bank. 5. if both banks are idle and cke is inactive(low level), then self refresh mode. 6. illegal if trcd is not met. 7. illegal if tras is not met. 8. must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. illegal if trrd is not met. 10. illegal for single bank, but legal for other banks in multi-bank devices. 11. illegal for all banks. current state /cs /ras /cas /we address command action write l h l l ba, ca, ap write/writeap illegal 11 l l h h ba, ra act illegal 11 l l h l ba, ap pre/pall illegal 11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11 mode register accessing h x x x x dsel nop - enter idle after tmrd l h h h x nop nop - enter idle after tmrd l h h l x bst illegal 11 l h l h ba, ca, ap read/readap illegal 11 l h l l ba, ca, ap write/writeap illegal 11 l l h h ba, ra act illegal 11 l l h l ba, ap pre/pall illegal 11 l l l h x aref/sref illegal 11 l l l l opcode mrs illegal 11
rev. 1.3 / apr. 2001 16 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram cke function truth table note : when cke=l, all dq and dqs must be in hi-z state. 1. cke and /cs must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. all command can be stored after 2 clocks from low to high transition of cke. 3. illegal if clk is suspended or stopped during the power down mode. 4. self refresh can be entered only from the all banks idle state. 5. disabling clk may cause malfunction of any bank which is in active state. current state cken- 1 cken /cs /ras /cas /we /add action self refresh 1 h x x x x x x invalid l h h x x x x exit self refresh, enter idle after tsrex l h l h h h x exit self refresh, enter idle after tsrex l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop, continue self refresh power down 2 h x x x x x x invalid l h h x x x x exit power down, enter idle l h l h h h x exit power down, enter idle l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop, continue power down mode all banks idle 4 h h x x x x x see operation command truth table h l l l l h x enter self refresh h l h x x x x exit power down h l l h h h x exit power down h l l h h l x illegal h l l h l x x illegal h l l l h x x illegal h l l l l l x illegal l l x x x x x nop any state other than above h h x x x x x see operation command truth table h l x x x x x illegal 5 l h x x x x x invalid l l x x x x x invalid
rev. 1.3 / apr. 2001 17 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram simplified state diagram mrs sref srex pden pdex act aref pdex pden bst read write write writeap writeap read readap readap pre(pall) pre(pall) pre(pall) command input automatic sequence idle auto refresh pre - charge power - up power applied mode register set power down write with autopre - charge power down write read with autopre - charge bank active read self refresh
rev. 1.3 / apr. 2001 18 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram power-up sequence and device initialization ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. power must first be applied to vdd, then to vddq, and finally to vref (and to the system vtt). vtt must be applied after vddq to avoid device latch-up, which may cause permanent dam- age to the device. vref can be applied anytime after vddq, but is expected to be nominally coincident with vtt. except for cke, inputs are not recognized as valid until after vref is applied. cke is an sstl_2 input, but will detect an lvcmos low level after vdd is applied. maintaining an lvcmos low level on cke during power-up is required to guarantee that the dq and dqs outputs will be in the high-z state, where they will remain until driven in normal oper- ation (by a read access). after all power supply and reference voltages are stable, and the clock is stable, the ddr sdram requires a 200us delay prior to applying an executable command. once the 200us delay has been satisfied, a deselect or nop command should be applied, and cke should be brought high. following the nop command, a precharge all command should be applied. next a extended mode register set command should be issued for the extended mode register, to enable the dll, then a mode register set command should be issued for the mode register, to reset the dll, and to program the operating parameters. 200 clock cycles are required between the dll reset and any command. during the 200 cycles of ck, for dll locking, executable commands are disallowed (a deselect or nop command must be applied). after the 200 clock cycles, a precharge all command should be applied, placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. additionally, a mode register set command for the mode register, with the reset dll bit deactivated (i.e. to program operating parameters without resetting the dll) must be performed. following these cycles, the ddr sdram is ready for normal operation. 1. apply power - vdd, vddq, vtt, vref in the following power up sequencing and attempt to maintain cke at lvc- mos low state. (all the other input pins may be undefined.) ? vdd and vddq are driven from a single power converter output. ? vtt is limited to 1.44v (reflecting vddq(max)/2 + 50mv vref variation + 40mv vtt variation. ? vref tracks vddq/2. ? a minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the vtt supply into any pin. ? if the above criteria cannot be met by the system design, then the following sequencing and voltage relation- ship must be adhered to during power up. 2. start clock and maintain stable clock for a minimum of 200usec. 3. after stable power and clock, apply nop condition and take cke high. 4. issue extended mode register set (emrs) to enable dll. 5. issue mode register set (mrs) to reset dll and set device to idle state with bit a8=high. (an additional 200 cycles of clock are required for locking dll) 6. issue precharge commands for all banks of the device. voltage description sequencing voltage relationship to avoid latch-up vddq after or with vdd < vdd + 0.3v vtt after or with vddq < vddq + 0.3v vref after or with vddq < vddq + 0.3v
rev. 1.3 / apr. 2001 19 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram 7. issue 2 or more auto refresh commands. 8. issue a mode register set command to initialize the mode register with bit a8 = low. power-up sequence / clk clk vdd dqs dq ? s mrs aref pre nop mrs emrs pre nop code code code code code code code code code vddq vref cke cmd ba0,ba1 a10 addr dm ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? tvtd t=200usec tmrd 200 cycles of ck* trp trfc power up vdd and ck stable precharge all emrs set mrs set reset dll (with a8=h) precharge all 2 or more auto refresh mrs set (with a8=l) *200 cycles of ck are required (for dll locking) before any executabl e command can be applied. vtt trp tis tih
rev. 1.3 / apr. 2001 20 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram mode register set (mrs) the mode register is used to store the various operating modes such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is programed via mrs command. this command is issued by the low signals of /ras, /cas, /cs , /we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode register set command can be issued. two cycles are required to write the data in mode register. during the mrs cycle, any command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 rfu dr tm cas latency bt burst length a2 a1 a0 burst length sequential interleave 0 0 0 reserved reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 reserved reserved a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 1 1 1 reserved a7 test mode 0 normal 1 vendor test mode a8 dll reset 0 no 1 yes ba0 mrs type 0 mrs 1 emrs
rev. 1.3 / apr. 2001 21 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram burst definition burst length & type read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. the block is uniquely selected by a1-ai when the burst length is set to two, by a 2 -ai when the burst length is set to four and by a 3 -ai when the burst length is set to eight (where ai is the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in burst definitionon table burst length starting address (a2,a1,a0) sequential interleave 2 xx0 0, 1 0, 1 xx1 1, 0 1, 0 4 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 8 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 0, 1, 2, 3, 4, 5, 6, 7 7, 6, 5, 4, 3, 2, 1, 0
rev. 1.3 / apr. 2001 22 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram cas latency the read latency, or cas latency, is the delay, in clock cycles, between the registration of a read command and the availability of the first burst of output data. the latency can be programmed 2 or 2.5 clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. reserved states should not be used as unknown operation or incompatibility with future versions may result. dll reset the dll must be enabled for normal operation. dll enable is required during power up initialization, and upon return- ing to normal operation after having disabled the dll for the purpose of debug or evaluation. the dll is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. any time the dll is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued. output driver impedance control the normal drive strength for all outputs is specified to be sstl_2, class ii. i-v curves of the full strength driver is included in this document.
rev. 1.3 / apr. 2001 23 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram extended mode register set (emrs) the mode register is used to store the various operating modes such as /cas latency, addressing mode, burst length, burst type, test mode, dll reset. the mode register is program via mrs command. this command is issued by the low signals of /ras, /cas, /cs , /we and ba0. this command can be issued only when all banks are in idle state and cke must be high at least one cycle before the mode register set command can be issued. two cycles are required to write the data in mode register. during the the mrs cycle, any command cannot be issued. once mode register field is determined, the information will be held until resetted by another mrs command. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 rfu* 0** ds dll a0 dll enable 0 enable 1 diable ba0 mrs type 0 mrs 1 emrs a1 output driver impedance control 0 full strength driver 1 half strength driver * all bits in rfu address fields must be programmed to zero, all other states are reserved for future usage ** this part do not support /qfc function, a2 must be programmed to zero.
rev. 1.3 / apr. 2001 24 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram function description burst read and burst write burst read and burst write commands are initiated as listed in fig.1. before the burst read command, the bank must be activated earlier. after /ras to /cas delay (trcd), read operation starts. ddr sdram has been implemented with data strobe signal (dqs) which toggles high and low during burst with the same frequency as clock (clk, /clk). after cas latency (cl) which is defined as the interval between command clock and the first rising edge of the dqs, read data is launched onto data pin (dq) with reference to dqs signal edge. burst write command in another bank can be given with having activated that bank where /ras to /ras delay (trrd) is satisfied. write data is also referenced and aligned to the dqs signal sent from the memory controller. since all read operation bursts data out at both the rising and the falling of the dqs, double data bandwidth can be achieved, also for write data. fig.1. burst read and burst write / clk clk dqs dq burst length =4, cas latency =2 a0 a1 a2 a3 row_a col_a row_b row_a row_b col_b autopcg no pcg trcd trrd cl activate bank 0 read bank 0 activate bank 1 write bank 1 w/ autopcg bank 0 data - out b0 b1 b2 b3 bank 1 data - in cke / cs ra, ca ap ba / ras / cas / we dm bank 0 bank 1 bank 0 bank 1
rev. 1.3 / apr. 2001 25 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram burst read followed by burst read back to back read operation in the same or different bank is possible as shown in fig.2. following first read command, consecutive read command can be initiated after bl/2 ticks of clock. in other words, minimum earliest possible read command that does note interrupt the previous read data, can be issued after bl/2 clock is met. when read(b) data out starts, data strobe signal does not transit to hi-z but toggle high and low for read(b) data. fig.2. burst read followed by burst read burst write followed by burst write back to back write operation in the same or different bank is possible as shown in fig.3. following first write com- mand, consecutive write command can be initiated after bl/2 ticks of clock. in other words, minimum earliest possible write command that does note interrupt the previous write data, can be issued after bl/2 clock is met. when write(b) data in starts, data strobe signal does not transit to hi-z but toggle high and low for write(b) data. though the timing shown in fig.3. is based on tdqss=0.75*tck, minimum number of clock of bl/2 for back to back write can be applied when tdqss=1.25*tck. fig.3. burst write followed by burst write / clk clk cmd dqs dq read (a) read (b) a0 a1 b0 b1 b2 b3 read(b) data out starts burst length =4, cas latency =2 a2 a3 / clk clk cmd dqs dq write (a) write (b) a0 a1 b0 b1 b2 b3 write(b) data in starts burst length =4, cas latency =2 a2 a3 tdqss
rev. 1.3 / apr. 2001 26 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram burst read followed by burst write back to back read followed by write operation in the same or different bank is possible as shown in fig.4. following first read command, consecutive write command can be initiated after ru{cl+bl/2} ticks of clock. (ru=round up for half cycle of cas latency, such as 1.5 and 2.5). in other words, minimum earlist possible write command that does not interrupt the previous read data can be issued after ru{cl+bl/2} clock is met. fig.4. burst read followed by burst write burst write followed by burst read back to back write followed by read operation in the same or different bank is possible as shown in fig.5. following first write command, consecutive read command can be initiated after (bl/2+1+tdrl) ticks of clock. in other words, minimum earlist possible read command that does not interrupt the previous write data can be issued after (bl/ 2+1+tdrl) clock is met. fig.5. burst write followed by burst read / clk clk cmd dqs dq read (a) write (b) burst length =4, cas latency =2 a0 a1 a2 a3 b0 b1 b2 b3 b0 b1 b2 b3 / clk clk cmd dqs dq write (a) read (b) burst length =4, cas latency =2 a0 a1 a2 a3 tdrl tdrl is counted with respect to clk rising edge after last falling edge of dqs and dq data has elapsed
rev. 1.3 / apr. 2001 27 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram burst read terminated by another burst read read command terminates the previous read command and the data is available after cas latency for the new com- mand. minimum delay from a read command to next read command is determined by /cas to /cas delay (tccd). timing diagram is shown in fig.6. fig.6. burst read terminated by another burst read burst write terminated by another burst write write command terminates the previous write command and the data is available after cas latency for the new com- mand. fastest write command to next write command is determined by /cas to /cas delay (tccd). timing diagram is shown in fig.7. fig.7. burst write terminated by another burst write b0 b1 b2 b3 / clk clk cmd dqs dq read (a) read (b) burst length =4, cas latency =2 a0 a1 tccd read(a) is terminated and read(b) data out starts b0 b1 b2 b3 / clk clk cmd dqs dq write (a) write (b) burst length =4, cas latency =2 a0 a1 tccd write(a) is terminated and write(b) data in starts
rev. 1.3 / apr. 2001 28 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram burst read terminated by another burst write write command terminates the previous read command with the insertion of burst stop command that disables the previous read command. the burst stop command interrupts bursting read data and data strobe signal with the same latency as cas latency (cl). the minimum delay for write command after burst stop command is ru{cl} clocks irre- spective bl. the burst stop command is valid for read command only. fig.8. burst read terminated by another burst write burst write terminated by another burst read read command terminates the previous write command and the new burst read starts as shown in fig.9. the mini- mum write to read command delay is 2 clock cycle irrespective of cl and bl. if input write data is masked by the read command, dq and dqs input are ignored by the ddr sdram. it is illegal for a read command to interrupt a write with autoprecharge command. fig.9. burst write terminated by another burst read b0 b1 b2 b3 / clk clk cmd dqs dq read (a) write (b) burst length =4, cas latency =2 a0 a1 tccd write data starts bst (a) burst dqs & dq stop b0 b1 b2 b3 / clk clk cmd dqs dq write (a) read (b) burst length =4, cas latency =2 masked dm a0 a1 a2 a3
rev. 1.3 / apr. 2001 29 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram burst read with autoprecharge if a read with autoprecharge command is detected by memory component in clk(n), then there will be no commands presented to this bank until clk(n+bl/2+trp). internal precharging action will happen in clk(n+bl/2). fig.10. burst read with autoprecharge burst write with autoprecharge if a write with autoprecharge command is detected by memory component in clk(n), then there will be no com- mands presented to this bank until clk(n+bl/2+1+tdpl+trp). last data in to precharge delay time (tdpl) is needed to guarantee the last data has been written. tdpl is measured with respect to rising edge of clock where last falling edge of data strobe (dqs) and dq data has elapsed. internal precharging action will happen in clk(n+bl/2+1+tdpl) as shown in fig.11. fig.11. burst write with autoprecharge / clk clk cmd dqs dq read (a) act burst length =4, cas latency =2 a0 a1 a2 a3 w/ autopcg early termination is illegal here bl/2 + trp / clk clk cmd dqs dq write (a) act burst length =4, cas latency =2 a0 a1 a2 a3 w/ autopcg tdpl trp
rev. 1.3 / apr. 2001 30 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram precharge command after burst read the earlist precharge command can be issued after read command without the loss of data is bl/2 clocks. the pre- charge command can be given as soon as tras time is met. fig.12 shows the earlist possible precharge command can be issued for cl=2 and bl=4. fig.12. precharge command after burst read precharge command after burst write the earliest precharge command can be issued after write command without the loss of data is (bl/2+1+tdpl) ticks of clocks. the precharge command can be given as soon as tras time is met. fig.13 shows the earliest possible pre- charge command can be issued for cl=2 and bl=4. fig.13. precharge command after burst write / clk clk cmd dqs dq read (a) act burst length =4, cas latency =2 a0 a1 a2 a3 earliest precharge time without losing read data trp prechg / clk clk cmd dqs dq write (a) act burst length =4, cas latency =2 a0 a1 a2 a3 tdpl trp prechg tdpl is counted with respect to clk rising edge after last falling edge of dqs and dq data has elapsed issuing precharge here allows completion of entire burst write
rev. 1.3 / apr. 2001 31 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram precharge termination of burst read the burst read (with no autoprecharge) can be terminated earlier using a precharge command as shown in fig.14. this terminates read data when the remaining elements are not needed. it allows starting precharge early. the pre- charge command can be issued any time after burst read command when tras time is met. activation or other com- mands can be initiated after trp time. fig.14. precharge termination of burst read precharge termination of burst write the burst write (with no autoprecharge) can be terminated earlier using a precharge command along with the write mask (dm) as shown in fig.15. this terminates write data when the remaining elements are not needed. it allows starting precharge early. precharge command can be issued after last data in to precharge delay time (tdpl). tdpl is measured with respect to rising edge of clock where last falling edge of data strobe (dqs) and dq data has elapsed. dm should be used to mask the remaining data (a2 and a3 for this case). tras time must be met to issue the pre- charge command. fig.15. precharge termination of burst write / clk clk cmd dqs dq read (a) act burst length =4, cas latency =2 a0 a1 precharge time can be issued here with trasmin being met trp prechg / clk clk cmd dqs dq write (a) prechg burst length =4, cas latency =2 masked dm a0 a1 a2 a3 act tdqss trp tdpl tdpl is counted with respect to clk rising edge after last falling edge of dqs and dq data has elapsed write burst is terminated early. dm is asserted to prevent locations of a2 and a3
rev. 1.3 / apr. 2001 32 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram dm masking (write) dm command masks burst write data with reference to data strobe signal and it is not related with read data. dm com- mand can be initiated at both the rising edge and the falling edge of the dqs. dm latency for write operation is zero. for x16 data i/o, ddr sdram is equipped with ldm and udm which control lower byte (dq0~dq7) and upper byte (dq8~dq15) respectively. fig.16. dm masking (write) burst stop command (read) when /cs=l, /ras=h, /cas=h and /we=l, ddr sdram enter into burst stop mode, which bursts stop read data and data strobe signal with reference to clock signal. bst command can be initiated at the rising edge of the clock as other commands do. bst command is valid for read operation only. bst latency for read operation is the same as cl. fig.17. burst stop command (read) / clk clk cmd dqs dq write (a) burst length =4, cas latency =2 masked dm a0 a1 a2 a3 tdqss dm can mask write data with reference to dqs dm write latency = 0 masked / clk clk cmd dqs dq read (a) burst length =4, cas latency =2 a0 a1 burst dqs & dq stop bst (a)
rev. 1.3 / apr. 2001 33 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram auto refresh and precharge all command when /cs=l, /ras=l, /cas=l and /we=h, ddr sdram enter into auto refresh mode, which executes refresh oper- ation with internal address increment. aref command can be initiated at the rising edge of the clock as other com- mands do. before entering auto refresh mode, all banks must be in a precharge state and aref command can be issued after trp period from precharge all command. fig.18. auto refresh and precharge all command self refresh entry and exit when cke=l, /cs=l, /ras=l, /cas=l and /we=h, ddr sdram enter into self refresh mode, which executes self refresh operation with internal address increment. before issuing self refresh command, all banks must be in a pre- charge state and cke must be low. sref command can be initiated at the rising edge of the clock as other commands do. because the clock buffer and internal dll circuit are disabled during self refresh state, self refresh exit (srex) should guarantee the stable input clock. therefore, a minimum of 200 cycles of stable input clock, where cke is held high, is required to lock the internal dll circuit of ddr sdram. a minimum tpdex (power down exit time) must be met before entering srex command. fig.19. self refresh entry and exit / clk clk cmd dqs dq cke prechg act precharge all trp autoref trc = tras + trp hi - z held high ? ? ? ? / clk clk cmd cke prechg act precharge all desl min. 200 clock cycles ? ? ? sref srex ? ? ? txsc tpdexmin
rev. 1.3 / apr. 2001 34 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram power down mode a power down mode can be achieved by asserting cke=l as shown in fig.20. there are two kinds of power down mode: 1. active and 2. precharge power down mode. the device must be in idle state and all banks must be closed before cke assertion in precharge power down mode. active power down mode can be initiated in row active state. the device will exit power down mode when cke is sampled high at the rising edge of the clock. fig.20. power down mode cke function since clock suspend mode in sdr sdram cannot be used in ddr sdram, it is illegal to issue cke=l during read or write burst. fig.21. cke function / clk clk cmd cke prechg act precharge power down mode ? ? ? pden pdex new command can be issued after power down exit / clk clk cmd dqs dq read (a) write (b) burst length =4, cas latency =2 a0 a1 a2 a3 b0 b1 b2 b3 cke transition of cke(to low) is illegal during burst read and write
rev. 1.3 / apr. 2001 35 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability dc operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. v ddq must not exceed the level of v dd . 2. v il (min) is acceptable -1.5v ac pulse width with < 5ns of duration. 3. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak to peak noise on vref may not exceed +/- 2% of the dc value. dc characteristics i (ta=0 to 70 c , voltage referenced to v ss = 0v) note : 1. vin = 0 to 3.6v, all other pins are not tested under vin =0v. 2. dout is disabled, vout=0 to 2.7v parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd relative to v ss v dd -0.5 ~ 3.6 v voltage on v ddq relative to v ss v ddq -0.5 ~ 3.6 v output short circuit current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 o c sec parameter symbol min typ. max unit note power supply voltage v dd 2.3 2.5 2.7 v power supply voltage v ddq 2.3 2.5 2.7 v 1 input high voltage v ih v ref + 0.15 - v ddq + 0.3 v input low voltage v il -0.3 - v ref - 0.15 v 2 termination voltage v tt v ref - 0.04 v ref v ref + 0.04 v reference voltage v ref 0.49*vddq 0.5*vddq 0.51*vddq v 3 parameter symbol min. max unit note input leakage current i li -5 5 ua 1 output leakage current i lo -5 5 ua 2 output high voltage v oh v tt + 0.76 - v i oh = -15.2ma output low voltage v ol - v tt - 0.76 v i ol = +15.2ma
rev. 1.3 / apr. 2001 36 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) 32mx4 parameter symbol test condition speed unit note -h -l operating current idd0 one ban; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 130 120 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 20 ma idle standby current i dd2f /cs=high, all banks idle; tck=tck(min); cke=high; address and control inputs changing once per clock cycle. vin = vref for dq, dqs and dm 40 ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) 25 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 50 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma tbd tbd ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle tbd tbd auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 310 self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal 2 ma low power 1 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition tbd tbd ma
rev. 1.3 / apr. 2001 37 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) 16m x8 parameter symbol test condition speed unit note -h -l operating current idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd ma operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 140 130 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 20 ma idle standby current i dd2f /cs=high, all banks idle; tck=tck(min); cke=high; address and control inputs changing once per clock cycle. vin = vref for dq, dqs and dm 40 ma active power down standby current i dd3p one bank active; power down mode; cke=low, tck=tck(min) 25 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc=tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 50 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma tbd tbd ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle tbd tbd auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & pc266b at 133mhz; distributed refresh 320 self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal 2 ma low power 1 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition tbd tbd ma
rev. 1.3 / apr. 2001 38 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram dc characteristics ii (ta=0 to 70 o c, voltage referenced to v ss = 0v) 8mx16 parameter symbol test condition speed unit note -h -l operating current idd0 one bank; active - precharge; trc=trc(min); tck=tck(min); dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle tbd tbd ma operating current i dd1 one bank; active - read - precharge; burst length=2; trc=trc(min); tck=tck(min); address and control inputs changing once per clock cycle 150 140 ma precharge power down standby current i dd2p all banks idle; power down mode; cke=low, tck=tck(min) 20 ma idle standby current i dd2f /cs=high, all banks idle; tck=tck(min); cke= high; address and control inputs changing once per clock cycle. vin=vref for dq, dqs and dm 40 ma active power down standby current i dd3p one bank active; power down mode; cke= low, tck=tck(min) 25 ma active standby current i dd3n /cs=high; cke=high; one bank; active-precharge; trc= tras(max); tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 50 ma operating current i dd4r burst=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); iout=0ma tbd tbd ma operating current i dd4w burst=2; writes; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck=tck(min); dq, dm and dqs inputs changing twice per clock cycle tbd tbd auto refresh current i dd5 trc=trfc(min) - 8*tck for ddr200 at 100mhz, 10*tck for ddr266a & ddr266b at 133mhz; distributed refresh 330 self refresh current i dd6 cke =< 0.2v; external clock on; tck=tck(min) normal 2 low power 1 ma operating current - four bank operation i dd7 four bank interleaving with bl=4, refer to the following page for detailed test condition tbd tbd ma
rev. 1.3 / apr. 2001 39 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram detailed test conditions for ddr sdram idd1 & idd7 idd1 : operating current: one bank operation 1. typical case : vdd = 2.5v, t=25 o c 2. worst case : vdd = 2.7v, t= 10 o c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changingt 50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl=2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop idd7 : operating current: four bank operation 1. typical case : vdd = 2.5v, t=25 o c 2. worst case : vdd = 2.7v, t= 10 o c 3. four banks are being interleaved with trc(min), burst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trrd = 2*tck, trcd= 3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3*tck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing 50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop
rev. 1.3 / apr. 2001 40 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram ac operating conditions (ta=0 to 70 o c, voltage referenced to v ss = 0v) note : 1. vid is the magnitude of the difference between the input level on ck and the input on /ck. 2. the value of vix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the s ame. ac operating test conditions (ta=0 to 70 o c, voltage referenced to vss = 0v) parameter symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals v ih(ac) v ref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals v il(ac) v ref - 0.31 v input differential voltage, ck and /ck inputs v id(ac) 0.7 v ddq + 0.6 v 1 input crossing point voltage, ck and /ck inputs v ix(ac) 0.5*v ddq -0.2 0.5*v ddq +0.2 v 2 parameter value unit reference voltage v ddq x 0.5 v termination voltage v ddq x 0.5 v ac input high level voltage (v ih , min) v ref + 0.31 v ac input low level voltage (v il , max) v ref - 0.31 v input timing measurement reference level voltage v ref v output timing measurement reference level voltage v tt v input signal maximum peak swing 1.5 v input minimum signal slew rate 1 v/ns termination resistor (r t ) 50 w series resistor (r s ) 25 w output load capacitance for access time measurement (c l ) 30 pf
rev. 1.3 / apr. 2001 41 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram ac characteristics (ac operating conditions unless otherwise noted) parameter symbol -h(ddr266b) -l(ddr200) unit note min max min max row cycle time t rc 65 - 70 - ns auto refresh row cycle time t rfc 75 - 80 - ns row active time t ras 45 120k 50 120k ns active to read with auto precharge delay t rap tras- (bl/2)xtck - tras- (bl/2)xtck - ns 16 row address to column address delay t rcd 20 - 20 - ns row active to row active delay t rrd 15 - 15 - ns column address to column address delay t ccd 1 - 1 - ck row precharge time t rp 20 - 20 - ns last data-in to precharge delay time (write recovery time) t dpl 15 - 20 - ns last data-in to read command t drl 1 - 1 - ck auto precharge write recovery + precharge time t dal 5 - 4 - ck 15 system clock cycle time cl = 2.5 t ck 7.5 15 10 15 ns cl = 2 10 15 10 15 ns clock high level width t ch 0.45 0.55 0.45 0.55 ck clock low level width t cl 0.45 0.55 0.45 0.55 ck data-out edge to clock edge skew t ac -0.75 0.75 -0.8 0.8 ns dqs-out edge to clock edge skew t dqsck -0.75 0.75 -0.8 0.8 ns dqs-out edge to data-out edge skew t dqsq - 0.5 - 0.6 ns data-out hold time from dqs t qh t hpmin -t qhs - t hpmin -t qhs - ns 1, 10 clock half period t hp t ch/l min - t ch/l min - ns 1,9 data hold skew factor t qhs - 0.75 - 1 ns 10 valid data output window t dv t qh -t dqsq t qh -t dqsq ns data-out high-impedance window from ck, /ck t hz -1.2 0.8 ns data-out low-impedance window from ck, /ck t lz -1.2 0.8 ns input setup time (fast slew rate) t is 0.9 - 1.2 - ns 2,3,5, 6 input hold time (fast slew rate) t ih 0.9 - 1.2 - ns 2,3,5, 6
rev. 1.3 / apr. 2001 42 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram n ote : 1. this calculation accounts for tdqsq(max), the pulse width distortion of on-chip circuit and jitter. 2. data sampled at the rising edges of the clock : a0~a11, ba0~ba1, cke, cs , ras , cas , we . 3. for command/address input slew rate >=1.0v/ns 4. for command/address input slew rate >=0.5v/ns and <1.0v/ns this derating table is used to increase tis/tih in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 5. ck, /ck slew rates are >=1.0v/ns 6. these parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. input setup time (slow slew rate) t is 1.0 - 1.2 - ns 2,4,5, 6 input hold time (slow slew rate) t ih 1.0 - 1.2 - ns 2,4,5, 6 input pulse width t ipw 2.2 - ns 6 write dqs high level width t dqsh 0.35 - 0.35 - ck write dqs low level width t dqsl 0.35 - 0.35 - ck clock to first rising edge of dqs-in t dqss 0.75 1.25 0.75 1.25 ck data-in setup time to dqs-in (dq & dm) t ds 0.5 - 0.6 - ns 6,7, 11~13 data-in hold time to dqs-in (dq & dm) t dh 0.5 - 0.6 - ns 6,7, 11~13 dq & dm input pulse width t dipw 1.75 - 2 - ns read dqs preamble time t rpre 0.9 1.1 0.9 1.1 ck read dqs postamble time t rpst 0.4 0.6 0.4 0.6 ck write dqs preamble setup time t wpres 0 - 0 - ck write dqs preamble hold time t wpreh 0.25 - 0.25 - ck write dqs postamble time t wpst 0.4 0.6 0.4 0.6 ck mode register set delay t mrd 2 - 2 - ck exit self refresh to any execute command t xsc 200 - 200 - ck 8 average periodic refresh interval t refi - 15.6 - 15.6 us input setup / hold slew-rate delta tis delta tih v/ns ps ps 0.5 0 0 0.4 +50 0 0.3 +100 0 parameter symbol -h(ddr266b) -l(ddr200) unit note min max min max
rev. 1.3 / apr. 2001 43 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram 7. data latched at both rising and falling edges of data strobes(ldqs/udqs) : dq, ldm/udm. 8. minimum of 200 cycles of stable input clocks after self refresh exit command, where cke is held high, is required to complete self refresh exit and lock the internal dll circuit of ddr sdram. 9. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tcl and tch). 10. thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl). tqhs consists of tdqsqmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. 11. this derating table is used to increase tds/tdh in case where the input slew-rate is below 0.5v/ns. input setup / hold slew-rate derating table. 12. i/o setup/hold plateau derating. this derating table is used to increase tds/tdh in case where the input level is flat below vre f +/-310mv for a duration of up to 2ns. 13. i/o setup/hold delta inverse slew rate derating. this derating table is used to increase tds/tdh in case where the dq and dqs slew rates differ. the delta inverse slew rate is calculated as (1/slewrate1)-(1/slewrate2). for example, if slew rate 1 = 0.5v/ns and slew rate2 = 0.4v/n then the delta inverse slew rate = -0.5ns/v. 14. dqs, dm and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tran- sitions through the dc region must be monotonic. 15. tdal = (tdpl / tck ) + (trp / tck ). for each of the terms above, if not already an integer, round to the next highest integer. tck is equal to the actual system clock cycle time. example: for ddr266b at cl=2.5 and tck = 7.5 ns, tdal = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) round up each non-integer to the next highest integer: = (2) + (3), tdal = 5 clocks 16. for the parts which do not has internal ras lockout circuit, active to read with auto precharge delay should be tras - bl/2 x tck. input setup / hold slew-rate delta tds delta tdh v/ns ps ps 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level delta tds delta tdh mv ps ps +280 +50 +50 (1/slewrate1)-(1/slewrate2) delta tds delta tdh ns/v ps ps 0 0 0 +/-0.25 +50 +50 +/- 0.5 +100 +100
rev. 1.3 / apr. 2001 44 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram capacitance (t a =25 o c, f=100mhz ) note : 1. vdd = min. to max., vddq = 2.3v to 2.7v, v o dc = vddq/2, v o peak-to-peak = 0.2v 2. pins not under test are tied to gnd. 3. these values are guaranteed by design and are tested on a sample basis only. output load circuit parameter pin symbol min max unit input clock capacitance ck, /ck c i1 2.0 3.0 pf delta input clock capacitance ck, /ck delta c i1 - 0.25 pf input capacitance all other input-only pins c i1 2.0 3.0 pf delta input capacitance all other input-only pins delta c i2 - 0.5 pf input / output capacitance dq, dqs, dm c io 4.0 5.0 pf delta input / output capacitance dq, dqs, dm delta c io - 0.5 pf v ref v tt v tt r t =50 w r t =50 w r s =25 w zo =50 w c l =30pf output
rev. 1.3 / apr. 2001 45 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram output drive characteristics (full strength driver) evaluation conditions: typical 25 o c (tambient), vddq=2.5v, typical process minimum 70 o c (tambient), vddq=2.3v, slow slow process maximum 0 o c (tambient), vddq=2.7v, fast fast process voltage pull down current (ma) pull up current (ma) nominal low nominal high minimum maximum nominal low nominal high minimum maximum 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 -10 0.2 12.2 13.5 9.2 18.2 -12.2 -14.5 -9.2 -20 0.3 18.1 20.1 13.8 26.0 -18.1 -21.2 -13.8 -29.8 0.4 24.1 26.6 18.4 33.9 -24.0 -27.7 -18.4 -38.8 0.5 29.8 33.0 23.0 41.8 -29.8 -34.1 -23.0 -46.8 0.6 34.6 39.1 27.7 49.4 -34.3 -40.5 -27.7 -54.4 0.7 39.4 44.2 32.2 56.8 -38.1 -46.9 -32.2 -61.8 0.8 43.7 49.8 36.8 63.2 -41.1 -53.1 -36.0 -69.5 0.9 47.5 55.2 39.6 69.9 -43.8 -59.4 -38.2 -77.3 1.0 51.3 60.3 42.6 76.3 -46.0 -65.5 -38.7 -85.2 1.1 54.1 65.2 44.8 82.5 -47.8 -71.6 -39.0 -93.0 1.2 56.2 69.9 46.2 88.3 -49.2 -77.6 -39.2 -100.6 1.3 57.9 74.2 47.1 93.8 -50.0 -83.6 -39.4 -108.1 1.4 59.3 78.4 47.4 99.1 -50.5 -89.7 -39.6 -115.5 1.5 60.1 82.3 47.7 103.8 -50.7 -95.5 -39.9 -123.0 1.6 60.5 85.9 48.0 108.4 -51.0 -101.3 -40.1 -130.4 1.7 61.0 89.1 48.4 112.1 -51.1 -107.1 -40.2 -136.7 1.8 61.5 92.2 48.9 115.9 -51.3 -112.4 -40.3 -144.2 1.9 62.0 95.3 49.1 119.6 -51.5 -118.7 -40.4 -150.5 2.0 62.5 97.2 49.4 123.3 -51.6 -124.0 -40.5 -156.9 2.1 62.8 99.1 49.6 126.5 -51.8 -129.3 -40.6 -163.2 2.2 63.3 100.9 49.8 129.5 -52.0 -134.6 -40.7 -169.6 2.3 63.8 101.9 49.9 132.4 -52.2 -139.9 -40.8 -176.0 2.4 64.1 102.8 50.0 135.0 -52.3 -145.2 -40.9 -181.3 2.5 64.6 103.8 50.2 137.3 -52.5 -150.5 -41.0 -187.6 2.6 64.8 104.6 50.4 139.2 -52.7 -155.3 -41.1 -192.9 2.7 65.0 105.4 50.5 140.8 -52.8 -160.1 -41.2 -198.2
rev. 1.3 / apr. 2001 46 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram output drive characteristics (full strength driver ) 0 20 40 60 80 100 120 140 160 0 0.5 1 1.5 2 2.5 maximum nominal high nominal low minimum pull down characteristics iout ( ma ) vout to v ssq ( v) -220 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 maximum nominal high nominal low minimum pull up characteristics iout ( ma ) v ddq to vout ( v)
rev. 1.3 / apr. 2001 47 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram timing diagram data input (write) timing (bl=4) data output (read) timing (bl=4) don?t care di n = data in for column n 3 subsequent elements of data in are applied in the programmed order following di n dqs dq dm tdqsl tdqsh tds tdh di n tdh tds tdqsck max dq n tqh /ck ck dqs dq tdqsq and tqh are only shown once, and are shown referenced to different edges of dqs, only for clarify of illustration. tdqsq and tqh both apply to each of the four relevant edges of dqs. tqhmin = thpmin - x where ; thp = minimum half clock period for any given cycle and is defined by clock high or clock low (tch, tcl) x consists of tdqsqmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
rev. 1.3 / apr. 2001 48 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram power down mode dqs dq dm enter power-down mode exit power-down mode don?t care nop valid* nop tis tck tch tcl tis tih tis addr command cke ck /ck valid valid vali tis tih tis tih ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ no column accesses are allowed to be in progress at the time power-down is entered. * = if this command is a precharge (or if the device is already in the idle state) then the power-down mode shown is precharge power down. if this command is an active (or if at least one row is already active) then the power-down mode shown is active power down.
rev. 1.3 / apr. 2001 49 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram auto refresh mode nop nop ar nop ar nop nop act valid ra /ck ck cke command dqs ba0,ba1 a10 tih tis tck tcl tch tis tih ra ba valid pre addr dq dm all banks one bank *bank(s) tis tih don?t care trp trfc trfc nop * = ? don?t care ?, if a10 is high at this point ; a10 must be high if more than one bank is active ( i.e., must precharge all a ctive banks) pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh. nop commands are shown for ease of illustration ; other valid commands may be possible at these times. dm, dq and dqs signals are all ?don?t care? / high-z for operation shown. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
rev. 1.3 / apr. 2001 50 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram self refresh mode tcl tck clock must be stable before exiting self refresh mode nop ar nop valid valid /ck ck cke command addr dqs dq dm tch tis tih tis tis tis tih tis tih trp* enter self refresh mode txsnr/ txsrd** exit self refresh mode don?t care * = device must be in the ?all banks idle? state prior to entering self refresh mode ** = txsnr is required before any non-read command can be applied, and txsrd (200 cycles of ck) are required before a read command can be applied. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
rev. 1.3 / apr. 2001 51 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram read without auto precharge nop read nop pre nop nop act nop nop nop valid valid valid col n ra ra ra bank x bank x dq dqs case 1: tac/tdqsck=min dq dqs /ck / ck cke don?t care dm ba0,ba1 a10 tih tih tis tck tcl tch tis tih tis tih tis tih cl = 2 trp ca, ra ra trpre trpst tdqsck min tlz min thz min do n tlz min tac min tlz max do n tlz max tac max thz max tis tih *bank x all banks one bank case 2: tac/tdqsck=max trpre trpst tdqsck max do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = ?don?t care?, if a 10 is high at this point pre = precharge, act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration ; other commands may be valid at these times cmd
rev. 1.3 / apr. 2001 52 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram read with auto precharge nop read nop nop nop nop act nop nop nop valid valid valid col n ra ra ra bank x bank x dq dqs case 1: tac/tdqsck=min dq dqs /ck ck cke cmd don?t care dm ba0,ba1 a10 tih tih tis tck tcl tch tis tih tis tih tis tih cl = 2 trp ca, ra ra trpre trpst tdqsck min tlz min thz min do n tlz min tac min tqpst tlz max do n tlz max tac max thz max en ap case 2: tac/tdqsck=max max tdqsck trpre trpst do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n en ap = enable autoprecharge, act = active, ra = row address nop commands are shown for ease of illustration ; other commands may be valid at these times
rev. 1.3 / apr. 2001 53 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram bank read access nop act nop nop nop read nop pre nop nop ra ra act col n ra ra ra bank x bank x bank x bank x ra tck tch tcl tis tih tis tih tis tih dis ap one bank all bank tis tih trc tras cl=2 trcd trp /ck ck cke cmd a10 ba0,ba1 dm case1: ra, ca ra trpre trpst tdqsck max thz max tac max tlz max tlz max dqs dq tac/tdqsck=min trpre trpst tdqsck min thz min tac min tlz min tlz min dqs dq case2 : tac/tdqsck=max dq n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following dq n dis ap = disable autoprecharge * = * ? don?t care?, if a10 is high at this point pre = precharge, act=active, ra=row address, ba=bank address nop commands are shown for ease of illustration; other commands may be valid at these times note that trcd > trcd min so that the same timing applies if autoprecharge is enabled (in which case tras would be limiting) dq n dq n don?t care
rev. 1.3 / apr. 2001 54 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram write without auto precharge nop write nop nop nop nop pre nop nop col n act ra bank x bank x tck tch tcl tis tih tis tih tis tih dis ap one bank all bank tis tih trp /ck ck cke cmd a10 ba0,ba1 ra, ca ra valid ra ra ba tdqss tdsh tdqsh twpst tdqsl twpres twpre tdpl dqs dq dm case 1 : tdqss = min di n dq dm dqs case 2 : tdqss = max tdqss twpres twpre tdqsl tdqsh tdss tdss twpst di n di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are provided in the programmed order following di n dis ap = disable autoprecharge * = * ? don?t care?, if a10 is high at this point pre = precharge, act=active, ra=row address, ba=bank address nop commands are shown for ease of illustration; other valid commands may be possible at these times don?t care
rev. 1.3 / apr. 2001 55 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram write with auto precharge nop write nop nop nop nop nop nop nop col n act ra bank x tck tch tcl tis tih tis tih en ap tis tih tdal /ck ck cke cmd a10 ba0,ba1 ra, ca ra valid ra ra ba tdqss tdsh tdqsh twpst tdqsl twpres twpre dqs dq dm case 1 : tdqss = min di n dq dm dqs case 2 : tdqss = max tdqss twpres twpre tdqsl tdqsh tdss tdss twpst di n valid valid di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following data in en ap = enable autoprecharge * = * ? don?t care?, if a10 is high at this point act=active, ra=row address, ba=bank address nop commands are shown for ease of illustration; other valid commands may be possible at these times don?t care
rev. 1.3 / apr. 2001 56 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram bank write access nop act nop nop write nop nop nop nop ra pre bank x tck tch tcl tis tih tis tih tis tih tdpl /ck ck cke cmd a10 ba0,ba1 ra, ca ra bank x tdqss tdsh tdqsh twpst tdqsl twpres twpre dqs dq dm case 1 : tdqss = min di n dq dm dqs case 2 : tdqss = max tdqss twpres twpre tdqsl tdqsh tdss tdss twpst di n col n ra ra tis tih bank x all banks one bank trcd tras dis ap di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following data in dis ap = disable autoprecharge * = * ? don?t care?, if a10 is high at this point pre=precharge, act=active, ra=row address nop commands are shown for ease of illustration; other valid commands may be possible at these times don?t care
rev. 1.3 / apr. 2001 57 hy5du28422t hy5du28822t HY5DU281622T 128mb (x4, x8, x16) double data rate sdram write dm operation nop write nop nop nop nop pre nop nop col n act ra bank x tcl tis tih tis tih dis ap tis tih tdpl /ck ck cke cmd a10 ba0,ba1 ra, ca ra ra ra ba tdqss tdsh tdqsh twpst tdqsl twpres twpre dqs dq dm case 1 : tdqss = min di n dq dm dqs case 2 : tdqss twpres twpre tdqsl tdqsh tdss tdss twpst di n valid tch tck one bank bank x all banks tis tih trp di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following data in (the second element of the four is masked) dis ap = enable autoprecharge * = * ? don?t care?, if a10 is high at this point pre=precharge, act=active, ra=row address, ba=bank address nop commands are shown for ease of illustration; other valid commands may be possible at these times don?t care tdqss = max

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